1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a circuit configuration for transmitting complementary signals.
2. Description of the Background Art
In an LSI (Large-Scale Integration), there is a case where a power supply voltage of an input/output buffer for transmitting/receiving a signal to/from the outside is different from that of an internal circuit for processing the signal. More specifically, there is a case where a high voltage is applied to the input/output buffer and a low voltage is applied to the internal circuit.
By setting the voltage supplied to the internal circuit to a low value, the following effects can be obtained. First, power consumption in the internal circuit can be suppressed. Second, when the voltage is lowered, an issue of a withstand voltage in a gate electrode of a transistor can be lightened. Consequently, the thickness of a gate oxide film in a transistor as a component of the internal circuit can be reduced. Third, by reducing the thickness of the gate oxide film, it is expected to increase the operating speed of the internal circuit.
In the case of supplying a high voltage to the input/output buffer and a low voltage to the internal circuit, a transistor having a thick gate oxide film has to be used for the input/output buffer and a transistor having a thin gate oxide film has to be used for a thin gate oxide film. At the time of supplying a signal to the internal circuit, the voltage of the signal has to be changed.
The configuration of the main portion of a conventional semiconductor integrated circuit will now be described with reference to FIG. 8. In the following, a CMOS (Complementary Metal-Oxide Semiconductor) LSI in which a power supply voltage at an input stage is 3.3 V and a power supply voltage in an internal circuit is 1.8 V will be described as an example. Each of input and output signals of the internal circuit is set at. a CMOS level.
The conventional semiconductor integrated circuit shown in FIG. 8 has: voltage transforming circuits 910 and 920 which receive signals IN and /IN complementary to each other supplied from the outside, respectively; and a signal transmitting circuit 900 including CMOS inverters 930 and 940 for inverting outputs of the voltage transforming circuits 910 and 920, signal lines L3 and L4, and CMOS inverters 950 and 960 for inverting outputs of the inverters 930 and 940. Outputs of the signal transmitting circuit 900 are supplied to an internal circuit (not shown) operated from a 1.8 V power supply.
The voltage transforming circuits 910 and 920 operate so as to drop the H level of the signals IN and /IN to around 1.8 V. The inverter 930 includes a PMOS transistor 803 and an NMOS transistor 804 each having a gate connected to an output node 801 of the voltage transforming circuit 910. The transistor 803 is connected between a power supply voltage of 1.8 V and a node 807. The transistor 804 is connected between a ground voltage and the node 807 (signal line L3).
The inverter 940 includes a PMOS transistor 805 and an NMOS transistor 806 each having a gate connected to an output node 802 of the voltage transforming circuit 920. The transistor 805 is connected between a power supply voltage of 1.8 V and a node 808. The transistor 806 is connected between a ground voltage and the node 808 (signal line L4).
The inverter 950 includes a PMOS transistor 811 and an NMOS transistor 812 each having a gate connected to the signal line L3. The transistor 811 is connected between a power supply voltage of 1.8 V and a node 115. The transistor 812 is connected between a ground voltage and the node 115.
The inverter 960 includes a PMOS transistor 813 and an NMOS transistor 814 each having a gate connected to the signal line L4. The transistor 813 is connected between a power supply voltage of 1.8 V and a node 116. The transistor 814 is connected between a ground voltage and the node 116.
When the H level of an output of each of the voltage transforming circuits 910 and 920 does not drop to 1.8 V, the output cannot be received by the transistor having the thin gate oxide film. The inverter 930 is therefore constructed by the transistors 803 and 804 adapted to 3.3 V and uses the power supply voltage of 1.8 V. Similarly, the inverter 940 is constructed by the transistors 805 and 806 adapted to 3.3 V and uses the power supply voltage of 1.8 V. On the other hand, a transistor adapted to 1.8 V is used as each of the transistors 811 to 814. To an internal circuit (not shown), signals of the nodes 115 and 116 are supplied.
The circuit configuration, however, has the following problems. When a deviation occurs between complementary signals, the deviation cannot be compensated by the cascaded configuration of the inverters.
The drivability of the transistor for 3.3 V is low (particularly, the drivability of a PMOS transistor is lower than that of an NMOS transistor). In order to raise the drivability, it is therefore necessary to widen the gate width of the transistor. When the drivability is compensated by the gate width, the gate width of the transistor is widened. It accordingly increases layout area and parasitic capacitance.
Generally, a transistor having high withstand voltage has a high threshold voltage relative to the withstand voltage. Specifically, a transistor for 3.3 V has a threshold voltage higher than that of a transistor for 1.8 V. An operating current (source-drain current) of a MOS transistor depends on a difference (Vgsxe2x88x92Vt) between a gate-source voltage Vgs and a threshold voltage Vt.
In inverters 930 and 940 constructed by the transistors for 3.3 V but driven on the source voltage of 1.8 V, therefore, the operating current of each of the MOS transistors cannot be sufficiently obtained. As a result, it deteriorates the operating speed of signal transmitting circuit 900.
As the amplitude of an output signal required by signal transmitting circuit 900, that is, the source voltage (1.8 V) of an internal circuit decreases, the more the problem becomes conspicuous. Particularly, when the source voltage of the internal circuit becomes lower than the threshold voltage of the transistors for 3.3 V for receiving outputs of voltage transforming circuits 910 and 920 at the front stage, signal transmitting circuit 900 becomes inoperable.
The present invention provides a semiconductor integrated circuit having a circuit capable of transmitting complementary signals at optimum timings without enlarging a layout area.
The present invention also provides a semiconductor integrated circuit having a circuit for changing the voltage amplitude of an input signal at high speed.
A semiconductor integrated circuit according to the present invention comprises: a first signal line for transmitting a first signal; a second signal line for transmitting a second signal substantially complementary to the first signal; first and second MOS transistors cross coupled between the first and second signal lines; a first logic gate including a third MOS transistor which receives a signal of the first signal line by its gate; and a second logic gate including a fourth MOS transistor which receives a signal of the second signal line by its gate.
Preferably, the semiconductor integrated circuit further has: a first terminal for receiving the first signal; a second terminal for receiving the second signal; a third logic gate including a fifth MOS transistor which is connected between the first terminal and the first signal line and is formed under process parameters different from those of the first to fourth MOS transistors; and a fourth logic gate including a sixth MOS transistor which is connected between the second terminal and the second signal line and is formed under process parameters different from those of the first to fourth MOS transistors.
Particularly, each of the first and second MOS transistors has a gate oxide film of which thickness is different from that of a gate oxide film in each of the fifth and sixth MOS transistors.
Particularly, a withstand voltage of each of the first and second MOS transistors is different from that of each of the fifth and sixth MOS transistors.
Particularly, the first and second MOS transistors are PMOS transistors, the first MOS transistor is connected between a power supply voltage line and the first signal line and its gate is connected to the second signal line, and the second MOS transistor is connected between the power supply voltage line and the second signal line and its gate is connected to the first signal line.
Particularly, the first and second MOS transistors are NMOS transistors, the first MOS transistor is connected between a ground voltage line and the first signal line and its gate is connected to the second signal line. The second MOS transistor is connected between the ground voltage line and the second signal line and its gate is connected to the first signal line.
Preferably, the first logic gate includes a seventh MOS transistor of a conductive type opposite to that of the third MOS transistor. The seventh and third MOS transistors form a first CMOS inverter. The second logic gate includes an eighth MOS transistor of a conductive type opposite to that of the fourth MOS transistor. The eighth and fourth MOS transistors form a second CMOS inverter. The third logic gate includes a ninth MOS transistor of a conductive type opposite to that of the fifth MOS transistor. The ninth and fifth MOS transistors form a third CMOS inverter. The fourth logic gate includes a tenth MOS transistor of a conductive type opposite to that of the sixth MOS transistor. The tenth and sixth MOS transistors form a fourth CMOS inverter.
In the semiconductor integrated circuit, therefore, the potentials of the signal lines can be driven at high speed by the cross-coupled MOS transistors which are disposed for the signal lines for transmitting signals which are complementary to each other. Consequently, a timing deviation between the complementary signals can be corrected.
Transistors each having a thick gate oxide film are used for the gate at the front stage, and transistors each having a thin gate oxide film are used for the gate at the rear stage and as the MOS transistors cross coupled. Alternately, transistors each having a withstand voltage higher than that of each of transistors used for the gate at the rear stage and as the cross-coupled MOS transistors are used for the gate at the front stage. With the configuration, even when the drivability of the gate at the front stage is low, the drivability can be compensated by the cross-coupled MOS transistors.
Another semiconductor integrated circuit of the invention has: a first signal line for transmitting an input signal set to have a first or second voltage; a second signal line for transmitting an level-shifted input signal which is set to have a second or third voltage; a first logic gate driven on the second and third voltages, for connecting one of the second and third voltages to a first node in response to the input signal; a level shifting auxiliary unit which operates in response to an inverted input signal and is activated when the first node and the third voltage are connected to each other by the first logic gate, to connect the third voltage and the first node; and a second logic gate driven on the second and third voltages, for connecting one of the second and third voltages to the second signal line in accordance with a voltage at the first node.
Preferably, the semiconductor integrated circuit further includes a leak current preventing unit for making the level shifting auxiliary unit inactive to isolate the third voltage and the first node from each other in the case where the first node and the second voltage are connected to each other by the first logic gate.
Preferably, a third logic gate driven by the first and second voltages, for inverting the input signal is further provided.
Preferably, the first logic gate includes a first MOS transistor for receiving the input signal by its gate; the second logic gate includes a second MOS transistor having a gate connected to the first node, the level shifting auxiliary unit includes a third logic gate for connecting the third or second voltage and a second node in accordance with the inverted input signal, and a third MOS transistor which has a gate connected to the second node and is connected between the third voltage and the first node, the third logic gate has a fourth MOS transistor for receiving the inverted input signal by its gate, and the first and fourth MOS transistors and the second and third MOS transistors are formed under different process parameters.
Particularly, the thickness of a gate oxide film of each of the first and fourth MOS transistors is different from that of each of the second and third MOS transistors.
Particularly, a withstand voltage of each of the first and fourth MOS transistors is different from that of each of the second and third MOS transistors.
Particularly, the semiconductor integrated circuit further includes a fifth MOS transistor which has a gate connected to the first node and is connected between the third voltage and the second node. The third and fifth MOS transistors are turned on/off complementarily to each other.
Particularly, the fifth MOS transistor is formed under process parameters similar to those of the third MOS transistor.
Preferably, the first and second logic gates are inverters.
Consequently, in the semiconductor integrated circuit, even when an input signal having a voltage level by which the operating speed of the first logic gate decreases is input, in response to the inverted input signal, the potential of the signal line can be driven by the MOS transistor as a component of the level shifting auxiliary unit. Thus, the level of an input signal can be shifted at high speed. Since the driving capability of the MOS transistor as a component of the first logic gate can be compensated, the gate width of the MOS transistor can be narrowed, so that the layout area and the parasitic capacity can be suppressed.
In the case where an input signal of the voltage level by which the operating speed of the logic gate does not decrease is input, the MOS transistor as a component of the level shifting auxiliary unit can be promptly turned off. With the configuration, the occurrence of a leak current can be prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.